The present invention relates to a manufacturing technology of a semiconductor device, in particular, to a technology effective when applied to a semiconductor device having a nonvolatile memory.
Some semiconductor devices have, therein, a nonvolatile memory circuit portion for storing data of a relatively small capacity to be used, for example, during trimming, data rescue or image adjustment of LCD (Liquid Crystal Device), or storing production number of the devices.
A semiconductor device having such a nonvolatile memory circuit portion is described, for example, in Japanese Unexamined Patent Publication No. 2001-185633 (Patent Document 1). This document discloses a single level•poly-EEPROM device which is an EEPROM (Electric Erasable Programmable Read Only Memory) device formed over a single conductive layer placed over a semiconductor substrate while being isolated therefrom via an insulating layer and can have a reduced area per bit.
Japanese Unexamined Patent Publication No. 2001-257324 (Patent Document 2) discloses a technology capable of improving the long-term data retaining capacity of a nonvolatile memory device formed by the single-layer poly-flash technology.
For example, in FIG. 7 of U.S. Pat. No. 6,788,574 (Patent Document 3), disclosed is a structure having a capacitor portion, a program transistor and a readout transistor, each isolated by an n well. In columns 6 and 7 of FIGS. 4A to 4C of Patent Document 3, disclosed is a constitution in which program/erase is effected by means of an FN tunneling current.